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Inter-Integrated Circuit
9.4.3
Address matching
All received addresses can be requested in seven-bit or 10-bit address. I 2 C address register 1, that contains
the I 2 C primary slave address, always participates in the address-matching process. If the GCAEN bit is
set, general call participates the address matching process. When the I 2 C module responds to one of the
above mentioned address, it acts as a slave-receiver and the IAAS bit is set after the address cycle.
Software needs to read the IICD register, after the first byte transfer, to determine that the address is
matched.
Start
TLOW:MEXT
ClkAck
TLOW:SEXT
TLOW:MEXT
ClkAck
Stop
TLOW:MEXT
SCL
SDA
Figure 9-11. I 2 C address matching
9.5
Resets
The I 2 C is disabled after reset. The I 2 C cannot cause an MCU reset.
9.6
Interrupts
The I 2 C generates a single interrupt.
An interrupt from the I 2 C module is generated when any of the events in Table 9-13 occur, provided the
IICIE bit is set. The interrupt is driven by bit IICIF (of the I 2 C status register) and masked with bit IICIE
(of the I 2 C control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt
routine.
You can determine the interrupt type by reading the status register. For SMBus time-outs interrupt, the
interrupt is driven by SLTF and masked with bit IICIE. The SLTF bit must be cleared by software by
writing 1 to it in the interrupt routine. You can determine the interrupt type by reading the status register.
NOTE
In master receive mode, the FACK must be set to 0 before the last byte
transfer.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
173
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